1. Field of the Invention
The present invention relates to a latch circuit in which a depletion type (or depletion mode) MIS transistor is connected either to an output node or to an input node thereof so that even if neither a set signal nor a reset signal is input when a power supply is activated, an output signal is stably fixed either in a set state or in a reset state, and to a semiconductor integrated circuit device provided with the latch circuit.
2. Description of the Related Art
Heretofore, a latch circuit for holding the state of detection of a signal generally has, when an RS latch circuit is used, a circuit configuration as shown in FIG. 9. The conventional latch circuit will hereinbelow be described with reference to FIG. 9.
First of all, a signal detecting circuit 2 detects a specific instruction input to a semiconductor integrated circuit device or detects an abnormality of a voltage appearing at a specific terminal or a power supply voltage, or an abnormality of a temperature thereof. A detection output signal SSETX is connected to a set terminal SX of a holding circuit such as a flip-flop such as an RS latch 1 which is active at the level “L”, and which is comprised of a 2-input NAND gate and a 3-input NAND gate. Upon detection of a specific instruction to a semiconductor integrated circuit device or detection of abnormality of a voltage or a temperature, the level of an output signal SCE of the 3-input NAND gate serving as an output signal of the RS latch 1 becomes “L”. At the same time, signals RRSTX1 and SRSTX2 input to a reset input terminal of the RS latch 1 are at the level “H”. An output signal of the RS latch is an enable signal of other circuits or systems. For example, upon recognition of a write instruction or a write enabling instruction to a nonvolatile memory device, the state of the circuit for generating a write start signal is placed in the enable state in accordance with the enable signal, or upon detection of short-circuit, abnormal heating or the like of a specific terminal, these circuits or systems are stopped in accordance with the enable signal.
When turning on the power supply, the RS latch 1 is reset in accordance with the signal SSRSTX1 as the output signal of the power-on-reset circuit 3, whereby right after turning on the power supply, the state of a write start signal generating circuit for generating a write start signal to a nonvolatile memory device is placed in a disable state, or in the case where the latch circuit is configured so that a signal detecting circuit detects a short-circuit, abnormal heating or the like of a specific terminal, the state of a controlled circuit is surely placed in the operation state to prevent a circuit or a system for remaining in the stop state right after turning on the power supply.
However, in general, power-on-reset circuits can not reliably generate reset signals in some cases when turning on the power supply.
In such a case, there is encountered a problem in that when turning on the power supply, the data in the nonvolatile memory device is rewritten into unintended data by mistake, or a circuit for which the power supply must be essentially activated in the operation state is stopped right after turning on the power supply.